1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter referred to as dynamic RAM) and particularly to a prevention of latch-up in a dynamic RAM including a peripheral circuit having a CMOS circuit.
2. Description of the Prior Art
FIG. 1 is a schematic sectional view showing a portion of a conventional dynamic RAM including a peripheral circuit having by a CMOS circuit (hereinafter referred to as CMOS DRAM).
A memory cell 1 of an nMOS type comprises a capacitor C3 for storing electric charges as data, the capacitor C3 having a storage gate electrode 2. The storage gate electrode 2 is connected to a Vcc/2 generating circuit 3 having a high impedance to decrease electric energy consumption of the CMOS-DRAM. A peripheral circuit 4 of a CMOS type, to which a power supply voltage Vcc is applied, is formed on a p-substrate 5, where the memory cell 1 is also formed, and on an n-well 22.
In addition, a voltage between the storage gate electrode 2 and the substrate 5 is lowered as a result of decrease of a voltage applied to the storage gate electrode 2 to a half of the power supply voltage Vcc and, accordingly, a thickness of an insulating film (not shown) of the capacitor C3 of the memory cell 1 can be made small without causing any damage thereto. Consequently, even if an area of the memory cell 1 is reduced, the capacitor C3 of the memory cell 1 has a large capacitance and large-scale integration can be attained with such CMOS DRAM.
In the above described CMOS DRAM, it is important to prevent latch-up in a parasitic thyristor (e.g., a pnpn structure formed by a p.sup.+ region 21, an n-well 22, the p-substrate 5 and an n.sup.+ region 23 shown in FIG. 1) existing in the peripheral circuit 4. Therefore, occurrence of latch-up during operation in the CMOS DRAM of FIG. 1 is prevented in the below described manner, thereby to avoid damage in the memory cell 1 and the peripheral circuit 4.
When the power supply voltage Vcc is applied to the peripheral circuit 4 to bring the CMOS DRAM into an enabled state, a negative voltage V1 is applied from a substrate voltage generating circuit (not shown) to the substrate 5. As a result, rise of the substrate voltage V.sub.BB is suppressed and transition to an on-state in the pnpn structure is prevented, whereby occurrence of latch-up can be avoided.
However, in this CMOS DRAM, the negative voltage V1 applied from the substrate voltage generating circuit to the substrate 5 is not stable immediately after the start of application of the power supply voltage Vcc and the unstable negative voltage V1 cannot suppress increase of the substrate voltage V.sub.BB. Thus, the negative voltage V1 does not have any substantial effect at the time of turn-on of the power supply and the substrate voltage V.sub.BB is increased according to the rise of the power supply voltage Vcc.
Now, let us consider a range of increase of the substrate voltage V.sub.BB at the time of turn-on of the power supply. First oi all, it is noticed that the substrate voltage V.sub.BB at this time is determined dependent on distribution of voltage between the power supply voltage Vcc applied to the n-well 22 and a ground level to which the n.sup.+ region 23 is connected. Accordingly, it is necessary to consider a pn junction capacitance C1 between the n-well 22 and the substrate 5 and a pn junction capacitance C2 between the substrate 5 and the n.sup.+ region 23. In addition, it is generally also necessary to take account of an influence caused by the existence of the capacitor C3 between the Vcc/2 generating circuit 3 and the substrate 5.
However, because of the high impedance of the Vcc/2 generating circuit 3, a moving amount of electric charges to the capacitor C3 of the memory cell 1 is very small immediately after the start of application of the power supply voltage Vcc even if the potential of the substrate is increased. As a result, there is actually little influence caused by the existence of the capacitor C3 and the substrate voltage V.sub.BB immediately after the start of application of the power supply voltage Vcc is increased due to capacitance coupling of the two pn junction capacitances C1 and C2. If this state is specifically considered with reference to an equivalent circuit shown in FIG. 2, an increase rate c of the substrate voltage V.sub.BB with respect to the power supply voltage Vcc is estimated as follows: ##EQU1##
Thus, the substra V.sub.BB is increased with the large rate.
Consequently, the conventional CMOS DRAM involves a disadvantage that the substrate voltage V.sub.BB is considerably increased immediately after the start of application of the power supply voltage Vcc to cause latch-up as shown in FIGS. 3A and 3B.
A clamp circuit for preventing latch-up in an n-well CMOS device is described in IDEM, 1985, pp. 504-508 by D. Takacs et al.